China’s struggle to achieve self-sufficiency in the manufacturing of advanced integrated circuits (ICs) is increasingly well documented. Foreign firms control the high-end technologies along the supply chain. But for how much longer?
Last year the Chinese press estimated that their semiconductor sector was 15 years behind in lithography, a fundamental part of the chip production cycle. This pattern-making process (which guides where the transistors sit on the silicon wafers) is critically important, especially when advanced chips like Apple’s M1 chip are home to 16 billion transistors.
As we reported in WiC480, Dutch company ASML is the global leader in patterning machines and a key contributor to why Moore’s Law (a doubling of transistors per chip every year) still holds.
At the turn of the century ASML pioneered immersion lithography in which scientists found they could make 45 nanometre process nodes (one nanometre is equivalent to one billionth of a metre) by depositing fluid between the lithographic lens and the silicon wafer. Now the nodes are being made below 7nm with newer EUV (extreme ultraviolet lithography) technology that vaporises molten tin into plasma, creating radiation. A laser beam is then bounced through a series of mirrors inside a vacuum chamber, facilitating production of even more miniscule wafer patterns.
ASML’s CEO Peter Wennink has underlined the formidable barriers to entry that this technology presents. Manufacturing know-how is now concentrated in just a few places around the world in a “seamless ecosystem”, he explained at his company’s most recent earnings announcement. “If you think you can replicate that within a very short term – it’s simply not possible,” he added. “If governments are determined to do this, it will take years.”
China Everbright, a domestic brokerage, said something similar in a recent piece of research that claimed that China’s self-sufficiency ratios for g-line and i-line photoresist (two of the four types of light-sensitive material used in lithography) were just 20%. It reported an even lower 5% figure for KrF photoresist.
There are signs though that Chinese scientists are making some headway. Shanghai Micro Electronics Equipment is readying a DUV (deep ultraviolet) lithography scanner that will help China’s leading domestic foundry SMIC to make chips at 28nm. The tool does not rely on components made in the US, meaning that the Chinese will have achieved full localisation at a fairly advanced node. Another company, Changchun Optics is said to have cracked the science of EUV with a prototype machine of its own. No one knows how long it will take to commercialise the technology (and all this implies in mass-producing chips). But it suggests a shorter technology gap than 15 years.
A third firm has been buying up old ASML equipment to conduct lithography research. Shanghai Xinke said in a statement that its goal is to “break the foreign monopoly in high-end photoresist” and to help China “achieve its localisation goal”.
The Trump administration persuaded its Dutch counterpart to block ASML from selling advanced EUV machines to China three years ago. But a study from the US National Security Commission on Artificial Intelligence has demanded that more be done to restrict supply of DUV equipment as well. Its report recommends that Washington works with the governments of the Netherlands and Japan “to align the export licencing processes of all three countries regarding EUV and ArF DUV immersion lithography equipment, toward a policy of presumptive denial of licences for exports to China”.
This would extend the scope of the Wassenaar Agreement, which restricts exports of items with potential military uses. Current rules allow ASML to sell DUV immersion scanners into China that produce patterns with a minimum feature size above a 45nm threshold. But the US Commission believes that further export restrictions “would slow China’s efforts to domestically produce 7nm or 5nm chips at scale”.
ASML is also developing a next-generation EUV tool with high numerical aperture optics to take chip scaling into the next dimension below 3nm.
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